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A hardware implementation of a preemptive scheduling algorithm

Presentation of the Bachelor thesis (alle Studiengänge) by Karim Elsebaie

27th Aug 2019, 9.00 AM, APB 1096

The recent trend of complex tasks operating on hardware is achieving tremendous results.The performance of these tasks are high. However, this results in area overhead and high power consumption. This thesis aims to find a method that reduces the are overhead and the power consumption. The technique of partial reconfiguration, that is a feature in Xilinx Field-Programmable Gate Arrays (FPGAs), can be used to reduce the area overhead and power consumption. As a result, an implementation is needed that can manage tasks and reconfigure the tasks according to their priorities.This thesis aims to implement a hardware scheduler for preemptive algorithms. The implemented scheduler manages the tasks with a scheduling algorithm compatible for hardware applications. It also supports partial reconfiguration. The partial reconfiguration is investigated in order to reconfigure tasks, resulting in less hardware overhead. The preemption system used in the proposed design is generic and can be applied to different applications. A use case operating in real-time is implemented and is tested with the scheduler. The test aims to check the performance of the scheduler, along with the preemption of the contexts of the use case and re-configuring the tasks inside the use case.The functionality of the scheduler is outstanding, since the tasks are scheduled according tot heir priorities in the system. The contexts of the use case are stored and restored correctly.As a result, the preemption system of the proposed design fulfilled the goal of the thesis. The utilization of the implemented design relies on the LUTs, as 55% of the LUTs are utilized in the design. The other resources have low utilization, as for example 5% of the BRAMs are used as memory in order to store the contexts in.

Realisierung eines RTOS-Schedulers auf dem Co-Prozessor eines Xilinx System-on-Chips

Presentation of the Bachelor thesis (alle Studiengänge) by Hendrik Kalberlah

9th Apr 2019, 2.30 PM, APB 1096

Im Rahmen der Bachelorarbeit wird die Auslagerung des Schedulers des Echtzeitbetriebssystems FreeRTOS auf einen Coprozessor untersucht. Durch die damit erreichte parallele Ausführung von Tasks und Scheduler lässt sich der bestehende Overhead im Betriebssystem reduzieren, da die für die Schedulingentscheidung notwendige Rechenzeit durch den Coprozessor bereitgestellt wird. Zur Realisierung der Aufgabenstellung wird in der Arbeit eine Kommunikationsstruktur aus Interrupts und gemeinsamer Speichernutzung entworfen. Zusätzlich wird ein Synchronisationsmechanismus implementiert, der die fehlerfreie und parallele Arbeitsweise des Systems unter Sicherstellung des wechselseitigen Ausschlusses innerhalb der kritischen Abschnitte der Anwendung garantiert. Das erarbeitete Konzept wird auf dem Dual-Core ARM-Cortex A9 eines PYNQ-Z1 Board implementiert, welches auf der Zynq-7000 SoC Plattform von Xilinx basiert. Die durch die Implementierung erzielten Ergebnisse werden durch Performanzmessungen anschließend evaluiert.

Heterogene Programmierung mit StarPU

Presentation of the student project (alle Studiengänge) by Robert Klemm

8th May 2018, 10.00 AM, APB 1096

StarPU ist eine Library welche Heterogene Programmierung, in C und Fortran ermöglicht. Dabei ist es möglich sowohl auf CPUs als auch auf GPUs parallel zu rechnen, wobei sich StarPU um die Lastverteilung kümmert. Dieser Vortrag stellt sein Task-basiertes Programmiermodell und die enthalten Schedulingalgorithmen vor. Dabei geht er auf Performance-Messungen auf Taurus ein.

Predictive Data Analytics for Energy Demand Flexibility

PhD defence by M. Sc. Bijay Neupane (Institut für Systemarchitektur, Professur Datenbanken)

27th Sep 2017, 3.00 PM, APB 1004 (Ratssaal)

The depleting fossil fuel and environmental concerns have created a revolutionary movement towards the installation and utilization of Renewable Energy Sources (RES) such as wind and solar energy. The RES entails challenges, both in regards to the physical integration into a grid system and regarding management of the expected demand. The flexibility in energy demand can facilitate the alignment of the supply and demand to achieve a dynamic Demand Response (DR). The flexibility is often not explicitly available or provided by a user and has to be analyzed and extracted automatically from historical consumption data. The predictive analytics of consumption data can reveal interesting patterns and periodicities that facilitate the effective extraction and representation of flexibility. The device-level analysis captures the atomic flexibilities in energy demand and provides the largest possible solution space to generate demand/supply schedules. The presence of stochasticity and noise in the device-level consumption data and the unavailability of contextual information makes the analytics task challenging. Hence, it is essential to design predictive analytical techniques that work at an atomic data granularity and perform various analyses on the effectiveness of the proposed techniques. The Ph.D. study is sponsored by the TotalFlex Project (http://www.totalflex.dk/) and is part of the IT4BI-DC program with Aalborg University and TU Dresden as Home and Host University, respectively. The main objective of the TotalFlex project is to develop a cost-effective, market-based system that utilizes total flexibility in energy demand, and provide financial and environmental benefits to all involved parties. The flexibilities from various devices are modeled using a unified format called a flex-offer, which facilitates, e.g., aggregation and trading in the energy market. In this regards, this Ph.D. study focuses on the predictive analytics of the historical device operation behavior of consumers for an efficient and effective extraction of flexibilities in their energy demands. First, the thesis performs a comprehensive survey of state-of-the-art work in the literature. It presents a critical review and analysis of various previously proposed approaches, algorithms, and methods in the field of user behavior analysis, forecasting, and flexibility analysis. Then, the thesis details the flexibility and flex-offer concepts and formally discusses the terminologies used throughout the thesis. Second, the thesis contributes to a comprehensive analysis of energy consumption behavior at the device-level. The key motive of the analysis is to extract device operation patterns of users, the correlation between devices operations, and influence of external factors in device-level demands. A novel cost/benefit trade-off analysis of device flexibility is performed to categorize devices into various segments according to their flexibility potential. Moreover, device-specific data preprocessing steps are proposed to clean device-level raw data into a format suitable for flexibility analysis. Third, the thesis presents various prediction models that are specifically tuned for device-level energy demand prediction. Further, it contributes to the feature engineering aspect of generating additional features from a demand consumption timeseries that effectively capture device operation preferences and patterns. The demand predictions utilize the carefully crafted features and other contextual information to improve the performance of the prediction models. Further, various demand prediction models are evaluated to determine the model, forecast horizon, and data granularity best suited for the device-level flexibility analysis. Furthermore, the effect of the forecast accuracy on flexibility-based DR is evaluated to identify an error level a market can absorb maintaining profitability. Fourth, the thesis proposes a generalized process for automated generation and evaluation of flex-offers from the three types of household devices, namely Wet-devices, Electric Vehicles (EV), and Heat Pumps. The proposed process automatically predicts and estimates times and values of device-specific events representing flexibility in its operations. The predicted events are combined to generate flex-offers for the device future operations. Moreover, the actual flexibility potential of household devices is quantified for various contextual conditions and degree days. Fifth, the thesis presents user-comfort oriented prescriptive techniques to prescribe flex-offers schedules. The proposed scheduler considers the trade-off between both social and financial aspects during scheduling of flex-offers, i.e., maximizing the financial benefits in a market and at the same time minimizing the loss of user comfort. Moreover, it also provides a distance-aware error measure that quantifies the actual performance of forecast models designed for flex-offers generation and scheduling. Sixth, the thesis contributes to the comprehensive analysis of the financial viability of device-level flexibility for dynamic balancing of demand and supply. The thesis quantifies the financial benefits of flexibility and investigates the device type specific market that maximizes the potential of flexibility, both regarding DR and financial incentives. Henceforth, a financial analysis of each proposed technique, namely forecast model, flex-offer generation model, and flex-offer scheduling is performed. The key motive is to evaluate the usability of the proposed models in the device-level flexibility based DR scheme and their potential in generating a positive financial incentive to markets and customers. Seven, the thesis presents a benchmark platform for device-level demand prediction. The platform provides the research community with a centralized repository of device-level datasets, forecast models, and functionalities that facilitate comparisons, evaluations, and validation of device-level forecast models. The results of the thesis can contribute to the energy market in materializing the vision of utilizing consumption and production flexibility to obtain dynamic energy balance. The developed demand forecast and flex-offer generation models also contribute to the energy data analytics and data mining fields. The quantification of flexibility further contributes by demonstrating the feasibility and financial benefits of flexibility-based DR. The developed experimental platform provide researchers and practitioners with the resources required for device-level demand analytics and prediction.

Routing on the Channel Dependency Graph: A New Approach to Deadlock-Free, Destination-Based, High-Performance Routing for Lossless Interconnection Networks

PhD defence by Dipl.-Math. Jens Domke

16th Jun 2017, 4.00 PM, APB 1004 (Ratssaal)

In the pursuit for ever-increasing compute power, and with Moore's law slowly coming to an end, high-performance computing started to scale-out to larger systems. Alongside the increasing system size, the interconnection network is growing to accommodate and connect tens of thousands of compute nodes. These networks have a large influence on total cost, application performance, energy consumption, and overall system efficiency of the supercomputer. Unfortunately, state-of-the-art routing algorithms, which define the packet paths through the network, do not utilize this important resource efficiently. Topology-aware routing algorithms become increasingly inapplicable, due to irregular topologies, which either are irregular by design, or most often a result of hardware failures. Exchanging faulty network components potentially requires whole system downtime further increasing the cost of the failure. This management approach becomes more and more impractical due to the scale of today's networks and the accompanying steady decrease of the mean time between failures. Alternative methods of operating and maintaining these high-performance interconnects, both in terms of hardware- and software-management, are necessary to mitigate negative effects experienced by scientific applications executed on the supercomputer. However, existing topology-agnostic routing algorithms either suffer from poor load balancing or are not bounded in the number of virtual channels needed to resolve deadlocks in the routing tables. Using the fail-in-place strategy, a well-established method for storage systems to repair only critical component failures, is a feasible solution for current and future HPC interconnects as well as other large-scale installations such as data center networks. Although, an appropriate combination of topology and routing algorithm is required to minimize the throughput degradation for the entire system. This thesis contributes a network simulation toolchain to facilitate the process of finding a suitable combination, either during system design or while it is in operation. On top of this foundation, a key contribution is a novel scheduling-aware routing, which reduces fault-induced throughput degradation while improving overall network utilization. The scheduling-aware routing performs frequent property preserving routing updates to optimize the path balancing for simultaneously running batch jobs. The increased deployment of lossless interconnection networks, in conjunction with fail-in-place modes of operation and topology-agnostic, scheduling-aware routing algorithms, necessitates new solutions to solve the routing-deadlock problem. Therefore, this thesis further advances the state-of-the-art by introducing a novel concept of routing on the channel dependency graph, which allows the design of an universally applicable destination-based routing capable of optimizing the path balancing without exceeding a given number of virtual channels, which are a common hardware limitation. This disruptive innovation enables implicit deadlock-avoidance during path calculation, instead of solving both problems separately as all previous solutions.

Hardware-Based Energy Accounting for Multi-Core Systems

Presentation of the Diploma thesis (alle Studiengänge) by Till Smejkal (Institut für Systemarchitektur, Lehrstuhl Betriebssysteme)

11th Apr 2016, 3.00 PM, APB 2101 Beratungsraum 2. Etage

In this talk I present I novel approach, which allows accurate low-overhead energy
measurements of individual programs or arbitrary groups of them on commercial
off-the-shelf multi-core hardware. The measurements are based on the Running Average
Power Limit processor feature available in recent Intel processors and utilize a
special scheduling algorithm to make accurate energy accounting possible.

Within the talk I will outline the different obstacles which had to be overcome to be
able to implement this technique in the Linux kernel as well as present energy
measurement results of various different benchmarks which show that the implemented
approach actually can deliver a high measurement accuracy while maintaining a low
runtime overhead.

Multi-Processor Look-Ahead Scheduling

Presentation of the Master thesis (alle Studiengänge) by Hannes Weisbach (Institut für Systemarchitektur, Lehrstuhl Betriebssysteme)

12th Feb 2016, 12.30 PM, APB E001

This talk presents ATLAS-MP, a combination of runtime and kernel scheduler, to process arbitrary collection of real-time jobs. ATLAS-MP inherits the accessible API and execution time prediction from the ATLAS infrastructure and extends it with primitives to express intra-task parallelism. The scheduler is able to take full advantage of SMP systems and balances load automatically over all available processors.

I compare benchmark results with the theoretical utilization bounds of ATLAS-MP and discuss current limitations as well as possible strategies to refine the design of ATLAS-MP.

Secure Virtualization of Latency-Constrained Systems

PhD defence by Dipl.-Inf. Adam Lackorzynski

6th Feb 2015, 11.10 AM, APB 1004 (Ratssaal)

Virtualization is a mature technology in server and desktop environments where multiple systems are consolidate onto a single physical hardware platform, increasing the utilization of todays multi-core systems as well as saving resources such as energy, space and costs compared to multiple single systems. Looking at embedded
environments reveals that many systems use multiple separate computing systems inside, including requirements for real-time and isolation properties. For example, modern high-comfort cars use up to a hundred embedded computing systems. Consolidating such diverse configurations promises to save resources such as energy and weight. In my work I propose a secure software architecture that allows consolidating multiple embedded software systems with timing constraints. The base
of the architecture builds a microkernel-based operating system that supports a variety of different virtualization approaches through a generic interface, supporting hardware-assisted virtualization and paravirtualization as well as multiple architectures. Studying guest systems with latency constraints with regards to virtualization showed
that standard techniques such as high-frequency time-slicing are not a viable approach. Generally, guest systems are a combination of best-effort and real-time work and thus form a mixed-criticality system. Further analysis showed that such systems need to export relevant internal scheduling information to the hypervisor to support
multiple guests with latency constraints. I propose a mechanism to export those relevant events that is secure, flexible, has good performance and is easy to use. The thesis concludes with an evaluation covering the virtualization approach on the ARM and x86 architectures and two guest operating systems, Linux and FreeRTOS, as
well as evaluating the export mechanism.

Erweiterung der Synthese von SpartanMC Beschleunigern um Software-Pipelining

Presentation of the Diploma thesis (alle Studiengänge) by Candy Lohse (Institut für Technische Informatik, Professur Eingebettete Systeme)

18th Dec 2014, 11.00 AM, APB 1096

Aufgrund ihrer flexiblen Anpassbarkeit an den jeweiligen Anwendungsbereich stellen auf FPGAs synthetisierte Softcore-Microcontroller eine Alternative zu herkömmlichen Systemen dar. Ein Beispiel für einen solchen Softcore ist der SpartanMC. Während der Software-Übersetzung für diesen Prozessor findet eine statische Analyse der enthaltenen Schleifen statt, auf deren Grundlage für geeignete Codeabschnitte Hardware-Beschleuniger als Prozessorerweiterungen generiert werden. Hierfür muss in Vorbereitung dieser Synthese ein Scheduling der betroffenen Operationen stattfinden.

Im Rahmen der vorgestellten Arbeit wurde Loop Pipelining durch die Entwicklung eines iterativen Modulo-Scheduling-Verfahrens als optionale Erweiterung des bestehenden List Scheduling-Algorithmus implementiert. Die Anwendbarkeit dieses Mechanismus hängt nicht von der Iterationszahl der Schleifen oder vom Zeitpunkt der Abbruchbedingung ab, sodass der Parallelisierungsgrad nicht durch schleifenvariante Durchlaufzahlen eingeschränkt wird. Unter Anwendung der spekulativen Ausführung paralleler Kontrollflusspfade ist im Gegensatz zu dem im GCC implementierten Verfahren auf RTL-Ebene auch die Verarbeitung von Schleifen möglich, die Verzweigungen enthalten. Weiterhin wurde gezeigt, dass mithilfe des implementierten Verfahrens der durch die Synthese erreichbare Speedup für geeignete Applikationen erhöht werden kann.

This event is sponsored by Professur für Eingebettete Systeme.

Energy Efficient Cloud Computing: Techniques and Tools

PhD defence by Dipl.-Inf. Thomas Knauth (Institut für Systemarchitektur, Professur für Systems Engineering)

16th Dec 2014, 4.00 PM, INF 1004 (Ratssaal)

Data centers hosting internet-scale services consume megawatts of power. Mainly for cost reasons but also to appease environmental concerns, data center operators are interested to reduce their use of energy. This thesis investigates if and how hardware virtualization helps to improve the energy efficiency of modern cloud data centers. Our main motivation is to power off unused servers to save energy. The work encompasses three major parts: First, a simulation-driven analysis to quantify the benefits of known reservation times in infrastructure clouds. Virtual machines with similar expiration times are co-located to increase the probability to power down unused physical hosts. Second, we propose and prototyped a system to deliver truly on-demand cloud services. Idle virtual machines are suspended to free resources and as a first step to power off the physical server. Third, a novel block-level data synchronization tool enables fast and efficient state replication. Frequent state synchronization is necessary to prevent data unavailability: powering down a server disables access to the locally attached disks and any data stored on them. The techniques effectively reduce the overall number of required servers either through optimized scheduling or by suspending idle virtual machines. Fewer live servers translates into proportional energy savings, as the unused servers no longer must be powered.

Practical Real-Time with Look-Ahead Scheduling

PhD defence by Dipl.-Inf. Michael Roitzsch

19th Sep 2013, 10.00 AM, INF 1004 (Ratssaal)

In my dissertation, I present ATLAS — the Auto-Training Look-Ahead Scheduler. ATLAS improves service to applications with regard to two non-functional properties: timeliness and overload detection. Timeliness is an important requirement to ensure user interface responsiveness and the smoothness of multimedia operations. Overload can occur when applications ask for more computation time than the machine can offer. Interactive systems have to handle overload situations dynamically at runtime. ATLAS provides timely service to applications, accessible through an easy-to-use interface. Deadlines specify timing requirements, workload metrics describe jobs. ATLAS employs machine learning to predict job execution times. Deadline misses are detected before they occur, so applications can react early.

Implementierung eines Schedulings mit dynamischer Last-verteilung für die SHAP-Mehrkernarchitektur

Presentation of the Diploma thesis by Peter Ebert (Institut für Technische Informatik, Professur für VLSI-Entwurfssysteme, Diagnostik und Architektur)

12th Feb 2013, 3.00 PM, INF 1096 (Beratungsraum, 1. Etage)

Die aktuelle SHAP-Version besitzt separate Round-Robin-Thread-Scheduler für jeden Kern. Dabei weilt ein Thread stets auf dem Kern, auf dem er gestartet wurde. Im Rahmen der Diplomarbeit soll diese Beschränkung zu Gunsten eines Lastverteilungsverfahrens aufgehoben werden. Zunächst wurde dazu ein neuer, auf dem Distributed-Weighted-Round-Robin-Algorithmus (DWRR) basierender Scheduler implementiert, der für jeden Kern die Scheduling-Runden mitzählt und zwei Thread-Listen anstatt einer verwendet. Der Garbage Collector des Systems soll während einer Thread-Migration nicht aktiv sein, um Konflikte im Stack zu vermeiden. Aus diesem Grund wird der Garbage-Collector-Bus, der alle Kerne verbindet, für die Thread-Übertragung genutzt. Trotz einer gegenwärtig noch fehlenden Eigenschaft erzielen die Leistungstests ein positives Ergebnis. Der maximale theoretische Speed-Up wird teilweise zu 99 Prozent erreicht. Und auch der Leistungsverlust für bereits ausgeglichene Systeme liegt lediglich bei wenigen Prozent. Mit der nachträglichen Einführung der fehlenden Eigenschaft und der Analyse verschiedener Kern- und Thread-Auswahlverfahren wird die Leistungsfähigkeit der neuen, migrationsfähigen SHAP-Version nochmals gesteigert werden können.

Measuring Energy Consumption for Short Code Paths Using RAPL

Academic talk by Marcus Hähnel (TU Dresden)

8th Jun 2012, 1.00 PM, E001

Measuring the energy consumption of software components is a major building block for generating models that allow for energy-aware scheduling, accounting and budgeting. Current measurement techniques focus on coarse-grained measurements of application or system events. However, fine grain adjustments in particular in the operating-system kernel and in application-level servers require power profiles at the level of a single software function. Until recently, this appeared to be impossible due to the lacking fine grain resolution and high costs of measurement equipment.

In this talk I present our experience in using the Running Average Power Limit (RAPL) energy sensors available in recent Intel CPUs for measuring energy consumption of short code paths. We investigated the granularity at which RAPL measurements can be performed and discuss practical obstacles that occur when performing these measurements on complex modern CPUs. Furthermore, we demonstrated how to use the RAPL infrastructure to characterize the energy costs for decoding video slices.

Clairvoyant Scheduling: Real-Time Support for Modern Applications

Scientific talk being part of the PhD defence (alle Studiengänge) by Michael Roitzsch (Institut für Systemarchitektur, Lehrstuhl Betriebssysteme)

12th Dec 2011, 11.30 AM, INF 1096 (Beratungsraum, 1. Etage)

From video and music to user interface animations, a lot of real-time workloads run on today’s desktops and mobile devices, but real-time scheduling interfaces in commodity operating systems have not gained traction. As a result, the CPU scheduler receives no explicit knowledge about applications’ needs and thus falls back to heuristics or best-effort operation.
A large body of real-time CPU scheduling research addresses this shortcoming, but developing applications within a real-time framework adds a burden for the developer: Best-effort computation adds no extra complexity, but results in weak real-time properties. Hard real-time environments offer strong guarantees, but are hard to develop and deploy. In my status talk, I will present existing approaches within this spectrum.
In my thesis, I want to explore a new point in this design space: clairvoyant scheduling based on work queues of upcoming jobs. In contrast to CPU scheduling, many I/O-devices today are organized using work queues, informing their specific scheduler about pending work items which it can inspect and order consciously. I want to research how to provide the CPU scheduler with similarly rich information, keeping the impact on the developer in mind by integrating with emerging trends of application development.
I propose a self-training scheduler, which uses deadlines to express timing requirements and lightweight application hints to express resource requirements. In my status talk, I will give an overview of my research idea, present my research agenda, and the evaluation already conducted using video playback as a dynamic high-throughput example load.

Betreuer: Prof. Dr. Hermann Härtig
Fachreferent: Prof. Dr. Christof Fetzer

Generische Re-Implementierung der Synthese von AMIDAR Funktionseinheiten

Presentation of the Diploma thesis (alle Studiengänge) by Michael Raitza (Institut für Technische Informatik, Professur Mikrorechner)

11th Nov 2011, 2.00 PM, INF 1005 (kleines Ratszimmer)

An der Professur für Mikrorechner wurde das Modell eines adaptiven Prozessors entwickelt, welcher sich zur Laufzeit and die spezifischen Anforderungen einer Applikation anpassen kann. Zu diesen Anpassungen zählt unter anderem die Synthese neuer Funktionseinheiten, welche dann auf einem Coarse-Grain-Reconfigurable-Array (CGRA) implementiert werden.
Im Rahmen dieser Arbeit soll der bestehende Synthese-Algorithmus so angepasst werden, sodass eine spätere Implementierung von Software-Pipelining möglich ist. Dazu ist es nötig den bestehenden Synthese-Algorithmus in großen Teilen zu re-implentieren. Zunächst sollen die erzeugten Datenflussgraphen hinsichtlich Ihrer Eignung für das Modulo-Scheduling untersucht und angepasst werden.
Weiterhin soll es möglich sein die Ausprägung des CGRA hinsichtlich der unterstützten Operationen zu definieren. Diese Definition soll die Anzahl und Ausprägung der im CGRA enthaltenen Operatoren enthalten. Die hierdurch definierten Beschränkungen sollen als Eingabe für den Synthese-Algorithmus verwendet werden.

This event is sponsored by Professur Mikrorechner.

Entwicklung eines Multiagentensystems auf Basis des Frameworks Jade zur Lösung komplexer Schedulingprobleme

Presentation of the Diploma thesis (alle Studiengänge) by Peter Hillmann (Institut für Angewandte Informatik)

28th Sep 2011, 10.15 AM, INF 2042

"Variable Neighborhood Search for Parallel Batch Machine Scheduling in Semiconductor Manufacturing"

Presentation of the Diploma thesis (alle Studiengänge) by Jiaqing Zhang (Institut für Angewandte Informatik)

7th Jul 2011, 9.00 AM, INF 1096

Frau Zhang hatten zur Aufgabe, für einen wichtigen Maschinentyp in der Halbleiterfertigung, den Batch-Tools, eine Heuristik zur Reihenfolgensteuerung zu untersuchen. Sie wurden von Robert Kohn betreut.

Provable Protection of Confidential Data in Microkernel-Based Systems

PhD defence by Dipl.-Inform. Marcus Völp

31st Jan 2011, 4.00 PM, INF 1004 (Ratssaal)

Today's mobile, desktop, and server systems process inceasing amounts of high-value personal, commercial or industrial data. Yet, despite over 30 years of academic and industrial efforts, the provable protection of confidential data against leakage over covert channels is still an issue. This dissertaion's thesis is to combine the complementary strength of microkernel-based systems and security-type-system-based static analyzes to provably protect confidential data in open microkernel-based systems. The two central contributions of this thesis are a non-interference-secure budget-enforcing fixed-priority scheduler that prevents leakage over scheduling-related timing channels while it preserves the real-time properties of the threads it scheduler; and a sound security-typesystem-based static analysis to prove the absence of security-policy violating information flows in the low-level operating-system code of microkernel-based systems.

Scheduling Issues in Mixed-Criticality Systems

Academic talk by Sanjoy Baruah (The University of North Carolina at Chapel Hill)

6th Jan 2011, 3.00 PM, INF E006

Please note: Televorlesung

Implementierung und Evaluation von Heuristiken aus dem Gebiet Evolutionary Computation zur Lösung komplexer Schedulingprobleme

Presentation of the student project (alle Studiengänge) by Peter Hillmann (Institut für Angewandte Informatik)

20th Dec 2010, 1.00 PM, INF 1096

Ziel der Arbeit war es, für ein Ablaufplanungsproblem bei Cluster Tools in der Halbleiterfertigung verschiedene evolutionäre Ansätze zu vergleichen.

Entwicklung eines generischen Frameworks zur Realisierung einer Thread-Verwaltung in AMIDAR-Prozessoren

Presentation of the Diploma thesis by Changgong Li (Institut für Technische Informatik, Professur Mikrorechner)

10th May 2010, 11.00 AM, INF 1096 (Beratungsraum, 1. Etage)

An der Professur Mikrorechner wurde das Modell eines adaptiven Prozessors entwickelt. Dieses Modell erlaubt es dem Prozessor zur Laufzeit einer Applikation auf deren spezifische Anforderungen zu reagieren. Hierzu zählen sowohl die Anpassung von Busstruktueren, als auch die Anpassung von bestehenden und die Synthese von neuen Funktionseinheiten.
Im Rahmen dieser Arbeit soll der existierender Simulator einer JVM auf AMIDAR-Basis um Multi-Threading erweitert werden. Dafür muss das Monitor-Konzept implementiert und der Simulator um AMIDAR-spezifische Multi-Threading-Mechanismen erweitert werden, wie z.B. das Erzeugen und Beenden von Threads, die Implementierung der Bytecodes monitorenter und monitorexit, sowie der Implementierung geeigneter Scheduling Mechanismen in der zentralen Steuerung des AMIDAR Simulators.

Integrating an External OSGi-based Scheduling Framework with a Commercial Factory Simulation Tool

Presentation of the Diploma thesis (alle Studiengänge) by Cornelius Hald (Institut für Angewandte Informatik)

26th Mar 2010, 10.00 AM, INF 1096

Ziel der Arbeit war es, ein von Herrn Hald entwickeltes Schedulingframework an den kommerziellen Fabriksimulator Factory Explorer anzudocken und ihn damit zu kontrollieren, obwohl er dafür eigentlich nicht vorgesehen ist.

The Barrelfish OS for Heterogeneous Multicore Systems

Academic talk by Andrew Baumann (ETH Zürich)

8th Apr 2009, 4.40 PM, INF E023

Barrelfish is a new open-source operating system for heterogeneous multicore systems being developed at ETH Zurich, in conjunction with Microsoft Research Cambridge. We seek to tackle two closely-related problems: scalability to many cores, and hardware diversity, which even in a single machine is increasing together with the available parallelism.

Barrelfish treats a multicore machine more as a networked system than as a single, monolithic computer, using an OS architecture we term "Multikernel". Each core runs an independent kernel instance, with cross-core consistency provided by user-space tasks employing ideas from distributed systems. We also apply knowledge-representation techniques to allow the OS and applications to reason about the richness of the hardware at runtime, and to control scheduling and resource allocation decisions.

This talk will discuss the implications of these ideas on the structure of an OS, and the current status and future directions of the system.

Process Scheduling in Modern Operating Systems

Scientific talk being part of the PhD defence by Dipl.-Inf. Boontawee Suntisrivaraporn

21st Jan 2009, 9.00 AM, INF 1004 (Ratssaal)

The process scheduler is one of the most prominent components in any operating systems. As the name suggests, its prime duty is to schedule a multiple number of processes for execution with limited computing resources, such as the CPU cycles and physical memory. Scheduling is typically done in such a way that parallelism of process execution is virtually attained despite the fact that the CPU can handle a single process at any instant of time. Moreover, it is concerned with deciding on policy that ensures fairness among processes, an effcient use of the CPU, short response time and high job throughput. In this talk, we present several scheduling algorithms, some of which are still in use in modern operating systems, and compare them by pointing out their drawbacks and advantages.

A Network Model Graph Editor for a Workforce Scheduling Tool

Presentation of the Diploma thesis (alle Studiengänge) by Tao Tang (Institut für Angewandte Informatik)

19th Jan 2009, 11.00 AM, INF 1096

Ziel der Arbeit war es, einen grafischen Editor für die Eingabe der Arbeitspläne für unser Montageplanungswerkzeug zu entwickeln.

Synthese von Controller Einheiten für AMIDAR Funktionseinheiten und Scheduling von

Presentation of the student project by Rico Backasch

15th Dec 2008, 9.45 AM, INF 1096

An der Professur Mikrorechner wurde das AMIDAR Modell eines adaptiven Prozessors entwickelt. Dieses Modell erlaubt es dem Prozessor seine internen Strukturen zur Laufzeit an die aktuelle ausgeführte Funktionseinheit anzupassen. Bisherige Arbeiten (www.amidar.de <http://www.amidar.de>) zeigen ein deutliches Beschleunigungspotential für Applikationen in eingebetteten Systemen.
Ziel dieser Arbeit ist es, den bestehenden Algorithmus für die Synthese von Funktionseinheiten zu erweitern. Dabei soll sowohl ein Scheduling für auszuführende Operationen errechnet werden, als auch ein Controller für synthetisierte Funktionseinheiten erzeugt werden. Weiterhin soll die Möglichkeit der Nutzung von Arrays und Objekten in synthetisierten Einheiten hinzugefügt werden. Ebenso soll ein Kostenmodell für die Hardwaresynthese erstellt werden und die Effektivität des Algorithmus an Hand von typischen Applikationen nachgewiesen werden.

Lösung von Schedulingproblemen mit reihenfolgeabhängigen Prozesszeiten unter Verwendung des Branch&Bound- und Filtered-Beam-Search-Ansatzes

Presentation of the student project (alle Studiengänge) by Steffen Seifert

10th Nov 2008, 11.15 AM, INF 1096

Ziel der Arbeit war es, Reihenfolgeprobleme unter der Bedingung reihenfolgeabhängiger Prozesszeiten zu untersuchen und anhand unterschiedlicher Ansätze zu lösen. Ein Anwendungsgebiet dieser Ansätze ist das Scheduling von Cluster Tools in der Halbleiterfertigung.

Entwicklung und Vergleich von Verfahren zur Lösung von Schedulingproblemen mit reihenfolgeabhängigen Prozesszeiten

Presentation of the student project (alle Studiengänge) by Tobias Uhlig

10th Nov 2008, 10.30 AM, INF 1096

Ziel der Arbeit war es, Reihenfolgeprobleme unter der Bedingung reihenfolgeabhängiger Prozesszeiten zu untersuchen und anhand unterschiedlicher Ansätze zu lösen. Ein Anwendungsgebiet dieser Ansätze ist das Scheduling von Cluster Tools in der Halbleiterfertigung.

Real-Time on Multicore – An Overview of Real-Time Computing Research at UNC

Academic talk by Björn Brandenburg (University of North Carolina, Chapel Hill)

29th Jul 2008, 1.00 PM, INF E023

The real-time systems group at the University of North Carolina at Chapel Hill focuses on developing techniques for implementing applications with real-time components on multicore platforms. This talk provides and overview of the four components of our research: (i) the development of real-time scheduling and synchronization algorithms; (ii) the development of techniques for validating timing constraints; (iii) the implementation of said algorithms in a real-time operating system (called LITMUS^RT, an extension of Linux); and (iv) the evaluation of proposed solutions under consideration of real-world overheads and constraints.

Real-Time Synchronization on Multiprocessors

Academic talk by Björn Brandenburg (University of North Carolina, Chapel Hill)

27th Jun 2007, 1.00 PM, INF E005

Real-time scheduling algorithms for multiprocessor systems have been the subject of considerable recent interest. For such an algorithm to be truly useful in practice, support for synchronization must be provided. However, for many global scheduling algorithms, no such mechanisms have been proposed. Furthermore, in the partitioned case, most prior semaphore schemes are either inefficient or restrict critical sections considerably. To address these issues, recent work at the University of North Carolina at Chapel Hill proposes the Flexible Multiprocessor Locking Protocol (FMLP). In this talk, we give an overview of the FMLP and take a look at some interesting analytical and empirical results on multiprocessor synchronization.

Scheduling Operating Systems

Presentation of the student project by Stephan Diestelhorst (Institut für Systemarchitektur, Lehrstuhl Betriebssysteme)

8th Jun 2007, 1.00 PM, INF E009

Hypervisor unterstützen die simultane Virtualisierung von mehreren Gastsystemen. Damit ergibt sich ein Bedarf für Scheduler, die die verschiedenen Gäste zeitlich (und räumlich) auf den vorhandenen physischen Ressourcen des Hostsystems einplant.

Die Verteidigung stellt meine Arbeit am Scheduler "sedf" in Xen vor, der sowohl harte Garantien gibt, als auch best-effort Zusagen machen kann. Besonderes Augenmerk liegt dabei auf der Unterstützung von schneller I/O, als Zusatz wird eine Erweiterung auf Mehrprozessorsysteme aufgezeigt.

Temporal and Spatial Mapping in Embedded Systems for Mobile Communications Systems

Academic talk by Bastian Ristau (Institut für Nachrichtentechnik)

19th Jan 2007, 1.00 PM, INF E006

As the complexity of signal processing algorithms is rising continuously, embedded systems are replacing single-chip solutions. Thus new strategies to partition and schedule algorithms for embedded systems at a very early design stage are required. The talk will cover modeling issues as well as optimization strategies for mapping and scheduling algorithms onto hardware.

Rechenzeitabstraktion durch kontengesteuertes Scheduling

Presentation of the Diploma thesis by Stefan Lebelt

6th Oct 2006, 1.00 PM, INF E06

In der ökonomischen Welt ist "Geld" ein grundlegendes Mittel der Abstraktion, das viele Probleme vereinfacht bzw. löst. Da in der Informatik nahezu überall abstrahiert wird um komplizierte Sachverhalte und Abläufe zu vereinfachen, scheint es sehr lukrativ zu sein, ökonomische Prinzipien auch hier in die Entwicklung von Systemarchitekturen einfließen zu lassen.

Das Dealmankonzept ermöglicht die kontenbasierte Verwaltung von beschränkten Ressourcen, indem jeder Ressource ein Preis zugeordnet werden kann, den Prozesse bei der Allokation bezahlen müssen. Die Dienste eines Dealmanservers ermöglichen Donation und Lending durch einfache Überweisung von "Geld" zwischen den Konten verschiedener Prozesse.

In dieser Arbeit wurde ein Schedulingmodell entworfen und prototypisch implementiert, das es ermöglicht, mit Hilfe des Dealmanansatzes von der Ressource CPU-Zeit zu abstrahieren. Damit konnte die Vereinfachung von Problemen und Mechanismen wie zum Beispiel Donation oder Denial-of-Service-Sicherheit erreicht werden. Es wurde zudem gezeigt, dass sich auf Basis von kontengesteuertem Scheduling ganz neue Lösungen bereits bekannter Probleme entwickeln lassen.

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Last modified: 6th Oct 2022, 2.51 PM
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